SoftBank’s SAIMEMORY and Intel Bet on Z-Angle Memory to Push Past HBM’s Next Wall

On February 2, 2026, SAIMEMORY, a wholly-owned subsidiary of SoftBank Corp., formalized a strategic collaboration with Intel to accelerate the development and commercialization of Z‑Angle Memory (ZAM). Positioned as a next-generation stacked DRAM solution, ZAM aims to address a central bottleneck in AI and HPC, memory performance under escalating power, thermal, and scaling constraints.

Intel describes ZAM as an architecture designed to surpass today’s High Bandwidth Memory (HBM) standards, signaling an intent not only to enhance memory capacity and bandwidth but also to optimize power efficiency for AI workloads. For enterprises and system architects, this represents a potential shift in how memory is conceptualized, moving beyond incremental improvements to a fundamentally rethought stack.

The Memory Bottleneck in AI & Why ZAM Matters

Modern AI accelerators are increasingly limited by memory rather than compute. The speed at which models can access and process data directly impacts performance, and as models grow in size, memory systems become critical to efficiency and scalability.

HBM has long been the industry solution, offering high bandwidth through stacked DRAM. Yet, as stack heights and densities increase, practical limits emerge: thermal dissipation, power density, packaging complexity, and manufacturability constrain further scaling. ZAM seeks to address these challenges through its “Z-axis” stacking concept, which reorients memory layers to improve thermal flow and energy efficiency while maintaining high density.

By potentially lowering energy consumption while preserving or increasing bandwidth, ZAM could offer significant operational and cost advantages for AI data centers and HPC deployments.

A distinguishing aspect of the Intel-SAIMEMORY partnership is its technical lineage. ZAM development leverages Intel’s Next Generation DRAM Bonding (NGDB) work, validated under the U.S. Department of Energy’s Advanced Memory Technology (AMT) program, which engaged national laboratories including Sandia, Lawrence Livermore, and Los Alamos. NGDB introduced innovative methods such as vertically bonded wafers and alternative interconnects, demonstrating experimentally that high-density DRAM stacks could achieve improved bandwidth and thermal performance. 

Roadmap to Commercialization: FY2027–FY2029

SoftBank’s announcement outlined a clear development timeline:

• • • Prototype phase: targeted for the fiscal year ending March 31, 2028 (FY2027)
    • Commercialization: aimed for FY2029, overlapping early 2030

This timeline frames ZAM as a near-future market entrant, giving enterprises and vendors a planning horizon for potential adoption in AI and HPC infrastructure. While ambitious, the schedule aligns with industry expectations for multi-year DRAM development cycles and signals a serious commitment to bringing next-generation memory to market.

The Intel-SAIMEMORY collaboration on Z‑Angle Memory represents a strategic, technically grounded attempt to overcome memory constraints in AI and HPC. With a foundation in NGDB and AMT research, a clear commercialization roadmap, and an ambitious design philosophy emphasizing capacity, bandwidth, and energy efficiency, ZAM is positioned as a potential industry inflection point. The next 3–4 years will reveal whether ZAM can move from lab-proven concept to practical, scalable, and commercially viable memory solution that could reshape the economics and architecture of AI infrastructure.