Meta Expands In-House AI Chip Roadmap With Broadcom as GenAI Inference Demand Accelerates

Key takeaways

• Meta said it is developing and deploying four new generations of MTIA chips within the next two years to support ranking, recommendations, and GenAI workloads.
• MTIA 300 is already in production for ranking and recommendation training, while MTIA 400, 450, and 500are positioned mainly for GenAI inference in the near term and into 2027.
• Reuters and WIRED reported that Meta worked with Broadcom on the latest chips and uses TSMC for manufacturing, signaling continued momentum behind hyperscaler custom silicon and AI infrastructure specialization.

Meta Deepens Vertical Integration in AI Infrastructure

Meta Platforms is expanding its in-house silicon program as AI infrastructure becomes a core competitive differentiator. The company’s MTIA (Meta Training and Inference Accelerator) roadmap reflects a strategic shift toward tightly integrated hardware-software stacks, optimized for its internal workloads.

Unlike traditional reliance on merchant GPUs, Meta is building application-specific accelerators designed around its largest compute demands, namely content ranking, ad delivery, and generative AI services. The company has already deployed hundreds of thousands of MTIA chips for inference workloads, indicating that custom silicon is no longer experimental but operational at hyperscale.

This move aligns with a broader industry transition where hyperscalers increasingly control their own silicon destiny to improve performance-per-watt, latency, and total cost of ownership.

The Immediate Focus Is Not All AI Workloads But Inference

One of the most important details in Meta’s announcement is the workload split. Meta said MTIA 300 is already in production and is being used for ranking and recommendation training. The next generations MTIA 400, 450, and 500 will be capable of handling broader workloads, but Meta said they will be used primarily for GenAI inference in the near future and into 2027.

Training still captures most headlines, but inference is increasingly where hyperscalers need scale, efficiency, and tighter cost control. Reuters reported that Meta plans to release the new chips at roughly six-month intervals, with company engineering leadership pointing to rapidly expanding infrastructure needs and surging inference demand.

The next phase of competition is not only about who can secure the most accelerators, but who can deploy the most efficient inference-optimized systems at scale. That has direct implications for chip architecture, memory bandwidth, thermal design, and rack-level integration.

Broadcom’s Role Underscores the Rise of Custom AI Silicon Partnerships

Meta’s official post did not name Broadcom, but Reuters reported that Meta contracts Broadcom to help with elements of the designs, while TSMC fabricates the processors. WIRED likewise reported that Meta partnered with Broadcom on the latest semiconductors and that the chips are built on RISC-V and manufactured by TSMC.

Hyperscalers are not simply buying AI chips but also increasingly co-developing specialized platforms with semiconductor partners. Broadcom’s own latest financial release supports that trend. On March 4, Broadcom said its Q1 FY2026 AI revenue reached $8.4 billion, up 106% year over year, driven by demand for custom AI accelerators and AI networking, and it guided to $10.7 billion in AI semiconductor revenue for the next quarter.

Rack-Scale Design, Liquid Cooling, and Memory Bandwidth Are Becoming Central

Beginning with MTIA 400, Meta has designed an entire system around the chips, roughly the size of several server racks, and that the design includes a form of liquid cooling. Meta also said the new chips are modular and can drop into existing rack system infrastructure, while staying aligned with industry standards such as PyTorch, vLLM, Triton, and Open Compute Project system and rack standards.

WIRED added that the MTIA roadmap is also being shaped by memory demands. MTIA 450 is expected to carry more high-bandwidth memory than MTIA 400, and that MTIA 500 is expected to push memory capacity further while adding low-precision data innovations. In practical terms, that suggests the competitive bottleneck in AI infrastructure is shifting beyond raw compute and deeper into memory bandwidth, power density, cooling, and system packaging. That conclusion is an inference based on the roadmap details reported by WIRED and Meta.

Meta’s announcement is less about replacing Nvidia outright and more about expanding a portfolio approach to AI infrastructure. Meta explicitly said it is sourcing silicon from multiple industry leaders while keeping MTIA at the center of its internal AI strategy. Meta’s February announcement of a long-term AMD partnership covering up to 6GW of AMD Instinct GPUs, which the company described as part of a more flexible and resilient infrastructure stack.

General-purpose AI accelerators will remain critical, but custom chips are gaining ground in workloads where efficiency, cost, and software-hardware alignment can be optimized at massive scale. Watch points may increasingly include HBM supply, advanced packaging capacity, liquid-cooling hardware, rack-scale integration, and foundry access rather than GPU unit counts alone.